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MP4651 off line led driver MP4651 rev.1.0 www.monolithicpower.com 1 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic technology descri ption the mp465 1 is a high p e rformance off-line led d r i v e r desig ned fo r pow ering th e le ds e s p e c i a l l y for high power isolated a pplication. the mp465 1 u t ilizes f i xed ope rat i n g f r eq uen cy p w m c o n t r o l . it outputs two 180 degree phase shifted driving signals for vario u s external power stag es. its enh anced 9v gate driver provides adequate driving capability for the external mosfets a nd directly drives th e external gate driving transformer. the MP4651 implements fast and high contrast ratio pwm dimming to the leds. pw m dimming is controlled with either an external dc voltage or pwm signa l. the burst dimming frequency can be synchronized to an externa l synchronizin g signal. the bu ilt- in fau l t man a gemen t fe at ure s inclu d e ope n led p r ote c t i o n , sh ort led p r ot ect i o n , ove r volta g e pr ote c t i o n , a nd over temper at ure prot ection . t he pr ot ectio n in ter f a c e is f l exible fo r vario u s se t ups an d is ea sy to u s e. mp465 1 int egr at es a delay t i mer t o re cov e r th e sy st em. the mp465 1 is available in a 16-pin soic package. features ? 9v en han ce d gat e dr ive r ? programma ble fixed operating fre quency ? input voltag e range from 9v to 30v ? dc or pw m input dimming control ? burst dimmi ng frequency synchron ization ? smart fault protection i n terface ? built-in fault manageme n t ? built-in delay timer for system recovery ? availa ble i n a soi c 1 6 pa ckage appli c ations ? lcd tv and lcd monito r ? flat panel video displays ? led lighting applicatio ns f o r m p s g r e e n st at us, pl eas e vis it mp s we bs it e un de r q u al it y assu ra nce . ?mp s ? an d ?t he f u ture o f ana l o g ic t e chno lo gy ? ar e re gi ste r ed tr ade ma r ks o f monolithic pow e r sy st em s , inc. t h e m p 4 6 5 1 i s c o ve r e d b y u s p a t e n t s 6,683,422, 6,316,881, an d 6,114,814. other pa tents pending. http://
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 2 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. simplifi ed typi cal applicati o n ci rcuit vin en di m 400v gnd 4 00v ref ref fb ov p 10 11 12 . . . fb ovp ocp pwmout pwm o u t syn c en fb vc c bf s f set ft gn d gl pwm o u t vi n gr ov p pw m i n co m p 1 2 3 4 5 6 7 8 9 MP4651 13 14 15 16 ssd sync sync syn c ocp 400v gnd
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 3 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) MP4651es soic16 MP4651es -20 c to +85 c * for tap e & reel, ad d suf f ix ?z (e.g. MP4651es?z ) for rohs co mpliant packaging, ad d su ffix ?lf (e.g. MP4651es? lf?z ) package reference ovp sync ssd fb gr gnd gl vcc 1 2 3 4 16 15 14 13 vin en pwmin bfs 12 11 10 9 comp ft pwmout fset 5 6 7 8 t op view pin 1 id absolute ma xi mum ratings (1) input voltag e v in .......................................... 35v gl, gr ......................................... -0.3v to 10.7v fb, ssd ....................................... - 5.8v to +5. 8 v other pins .................................... - 0.3v to +6. 5 v continuous power dissipation (t a = +25c) (2) ???? ? ???? ? ???? ? ???.2.5 w junction te mperature ............................... 150 c lead temperature (solder)....................... 260 c operating frequency .............. 20khz to 15 0khz storage temperature ............... - 55 c to +150 c recommended operating conditions (3) input voltag e v in ................................. 9v to 30v operating frequency (typical) ................ 50khz maxi mum j unction temp. (t j ) .............. +125 c thermal resistance (4) ja jc soic16 ................................... 80 ...... 30 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the maximum junction tempe r ature t j (max), the junction-to- ambient therm a l resistance ja , a nd the a m bient t e mperatu r e t a . the ma ximu m allow able cont inuous po w e r di ssipation at an y ambient tem peratur e is calculated b y p d (max)=(t j (max)- t a )/ ja . exceedi ng the m a ximum allow a ble po w e r dissipation w ill cause ex cessive die temperature, and the reg u l ator w ill go into thermal sh utdo w n . inte rnal thermal shutdo w n circuitr y protects the device from perma ne nt damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) measured on je sd51-7, 4 - la y e r pcb
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 4 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. electri c al characteristi cs v in = 12v, t a = +25 c, unless otherw ise noted . parameter sy mbol conditio n min t y p max units gate driver gl, gr gate pull- do wn r gd 2 ? gate pull-up r gu 4 ? output source curre n t i sour ce 1 a output sink curre n t i sink 2 a maximum duty cycle d ma x 46% en en turn on thre sh old v en-on 2 v en turn off thres h old v en-off 1 v internal pull-down re si sto r r en-in 60 k ? brightness dimming control range pwm full scale v pwm dc input burst dimming 1.1 1.2 1.3 v pwm logic input threshold v th-pwm pwm dimming 1.6 1.9 2.2 v pwm logic input hysteresis v th-pwm-h y st pwm dimmin g 0.1 v burst frequency set (bfs) source current i src ( bfs ) v bfs = 2v 120 140 170 a lower threshold v v ( bfs ) 2.2 2.4 2.6 v upper threshold v p ( bfs ) 3.3 3.55 3.8 v supply current supply cu rre nt (enable d ) i in-en no drive r out put 1.5 2.5 ma supply cu rre nt (disable d ) i in-off v in =30v 1 a operating frequency f o 25k ? fset to gnd 46.5 50 53.5 khz frequency set voltage v fset 1.14 1.2 1.25 v output pwm dimming signal for led (pwmout) logic high voltage v h-pwmout normal operation 5v 6 6.5v v logic low voltage v l-pwmout at fault cond ition, 25k ? fset to gnd 0.1 0.6v v output pwm source curre n t i sour ce pw m out 100pf o n pwmout pi n 3 ma output pwm sink cu rrent i sink p w m out 100pf o n pwmout pi n 20 ma led cur r en t feedba ck (f b) magnitud e |v fb | 0.57 0.6 0.63 v input re sistan ce r fb in 30 k ? over voltage protection (ovp) over voltage protectio n thre sh old v t h (ovp) 2.22 2.38 2.55 v
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 5 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. electri c al characteristi cs (con tinued ) v in = 12v, t a = +25 c, unless otherw ise noted . parameter sy mbol conditio n min t y p max units fault timer (ft) threshold v th ( ft ) 2.2 2.4 2.6 v source curre n t i source ( ft ) 8 a com p clamp volta g e v co m p 0.60 v referen c e current i co m p + 20 a pull down cu rre nt at fault condition i co m p- f ault fault mode i s triggered 30 a burs t freq u e nc y s y nchroniza tion (s ync) high logic lev e l v s y nc-h 1.4 v low logic lev e l v s y nc-l 0.7 v pulse wi dth t s y nc 6 10 20 s synchroni zin g freq uen cy f sync dc input burst dimming, comp ared to the freque ncy f bfs s e t by bfs pin r an d c 110% 120% fault dete cti on thresh old (ssd, fb) ssd thres hold v ssd 2.22 2.36 2.55 v ssd dete ctio n delay time t d ssd 7 s fb threshold v fb th 1.1 1.2 1.3 v fb detectio n delay time t df b 7 s outpu t ga te driv er (vcc) voltage v vcc no loa d 8.7 9.7 10.5 v cur r e n t i vcc 20 ma
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 6 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. pin functio n s pin # name description 1 ovp over voltage protection. t he output vol t age is sen s e d by this pin throug h a vol t age divider from the a n o de of the le d to groun d. if the voltage at ovp exce eds 2.38v for 7us, the fau l t mode is tri g g e red. 2 sync synchronization for the burst dimming frequency . applying a synchronizing signal with a narrow pulse on this pin will synchronize the burst frequency on bfs pin. the frequency of the synchronizing signal should be highe r than the frequency set by bfs pin. 3 ssd short string dete ction. a comp arator i s integrate d in this pin for short st ring p r otection. if the voltage on this pin gets lower than 2.36v for 7us, the fault mode is triggered. 4 fb led cu rrent feedb ack inp u t. conne ct this pin to the cathode of the led an d shu n t a sen s e resi sto r to gro und. the i n te rnal e r ror a m plifier si nks a curre n t from t he comp pin prop ortion al to the absolut e value of the voltage at this pin. the averag e voltage at this pin is regul ated to 0.6v refere nce voltage. the voltage on this pin is also used for shor t string detection. when the voltage on this pin gets higher than 1.2v for 7us, the ic recognizes th is as short string condition and triggers the fault mode. 5 comp feedback compensation node. connect a compensation capacitor or a r-c network from this pin to gnd. 6 ft fault timer. connect a timing capacitor from this pin to gnd to set the fault timer to recover the system. when the voltage on this pin gets higher than the 2.38v threshold, the ic recovers. 7 pwmout this pin outputs the pwm dimming signal to le d for fast dimming. at fault mode, the pwmout is pulled down. 8 fset frequency set. connect a resistor from this pi n to gnd. this resistor sets the operating frequency of the MP4651. a 25kohm resistor se ts the operating frequency at typical 50khz. 9 bfs burst frequency set. connect a resistor in parallel with a capacitor from bfs to gnd. the resistor and capacitor programs the burst dimmi ng frequency. if the burst dimming is to be controlled by an external pwm signal, pull up bfs to vcc through a 20k ? resistor and apply the pwm signal to the pwmin pin. 10 pwmin burst - mod e (digital) b r ight ness control input. for dc input bu rst di mming, the voltage rang e from 0 v to 1.2v at pwmin linea rly sets the burst-mode d u ty cycle from 0 to 100%. for external p w m input di m m ing, directly apply t he l o gic sign al on this pi n. th e mp465 1 h a s positive dimm ing pola r ity. 11 en enable input. pull en high to turn on th e chip, and pull en low to turn it off. 12 vin supply voltage input. 13 vcc linear regulator output and bias supply of the gate driver. it provides the supply for the gate driver and also the external control circui t, the typical value is 9.7v. bypass vcc with a 1 f or larger ceramic capacitor. 14 gl driving signal output, 180 degree phase shifted of gr 15 gnd ground. 16 gr driving signal output, 180 degree phase shifted of gl
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 7 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. block diagram ovp fb fset co m p 1 4 5 8 0.6v 2.38v ssd 3 2.36v p ul s e w i d t h m o dul at i on pw m i n 10 pw mout 7 dr iver en 11 ft 6 2. 38 v gr 16 ga te dr iv e r gl 14 vi n 12 r egu l a t or vcc 13 gm 1. 2v dc l/ r bfs 9 syn c 2 bu r s t dim m in g si gn al generator fault m a na ge m e n t figure 1?MP4651 block diagram
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 8 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. design information stead y state and enable control the mp465 1 is a fixed operating frequency off- line led driver, specifically designe d for the hig h power isolated applicat ions. powered by 9v t o 30v input supplies, the MP4651 outputs two 18 0 degree pha se shifte d driving sign als for the external power stages. its enhan ced 9v gat e driver provides adequat e driving ca pability to th e external mosfets a nd directly drives the external gate driving transformer. the mp46 51 utilizes pulse widt h modulation c o n t r o l t o t h e s y s t e m . the op era t ing fr eq uen cy is set by a n e x terna l re sistor co nne cte d fr om fse t p i n t o g n d . the led current is fe d back to f b pin and compared wit h internal 0.6v reference voltage. together with the integr ator compensation network on comp pin, which is connected t o the output of the error amplifier, the output led current is accurately regulated. t h e voltage on comp pi n is compared with the internal o s cillator and generates duty cycl e modulated signals to control the e x ternal power switches. the sy stem power is co ntro lled by en p i n. w h en the ch ip is e nab led , t he built -in re gu lator fo r vcc is power ed up and th e int e r nal cir c u i t sta r ts. brightness control MP4651 implements burst dimming (digital brightness) of the led. the mp465 1 has a built- in burst oscillator whi c h can gener ate a triang l e waveform o n the bfs p i n. burst dimming can be achieved by either a dc voltage input or extern al pwm signal. when burst dimming with a dc input voltag e, add a capacitor in parallel with a resistor on bf s pin to set th e burst frequency and apply the dc voltage on the pwmin pin to progr am the burst duty cycle. the burst fr equency ca n be synchr onized to a n external frequency. applying a synchronizin g frequency signal with narrow pulse on sync pi n can synchr onize the burst fre quency. the synchronizin g frequency should be higher than the burst frequency set by the bf s pin. please refer to sync pin description for det ails. when burst dimming with external pwm signal, pull up bfs pin to vcc through a 20k ? resi st or and apply the pwm signal on pwmin pin. fast and high contras t ratio pw m dimming the mp465 1 implemen ts fast and high contra st ratio pwm dimming to the wled. the pw m dimming signal (controlled by a dc input voltag e or direct pwm signal) is outputted on pwmout pin to drive the external mosf et in series wit h the leds, therefore th e led current rises u p immediately when pwm dimming signal is effective. the pwm dimming signal is a l so u s ed t o disconnect t he compensation netw o rk (on co mp pin, a capacitor or a r-c network) f r om the error amplifier at pwm off interval, and so that th e compensation network voltage is hold at th is interval and gets ne arly immediately to the steady state value when pwm signal is effective . it eliminates the control loop respo n se time an d realizes fa st dimming. the mp465 1 strict ly controls the se quence of th e driving sign als. both th e sequence of gl and gr signals an d the delay time b e tween pw m dimming signal and dr iving signa ls a r e accurate ly fixed. therefore, for each time of pwm dimmin g, the driving signals are exactly the same and so does the o u tput power delivered t o the load. it eliminates t he possibilit y of flicker at small pw m dimming pulse and thus realizes the h i g h contrast ratio pwm dimming. pw m o u t i led pw m i n co m p figure 2?fast and high contrast ratio pwm dimming
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 9 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. fault protection system fault management facilitie s include the over voltage protection , short string protectio n and a delay timer for system recovery. the output voltage is monitored by the ovp pi n through a voltage divid e r. once the voltage on ovp pin exceeds 2.38v for 7us, the mp465 1 recognizes this as ope n conditio n and trigge rs fault mode. the ssd pi n is used for short string detectio n . when the voltage on ssd pin get s lower than 2.36v for 7us, the MP4651 recognizes this a s short string condition an d triggers the fault mod e. fb pin also functions a s short strin g protection . when the voltage on f b pin is hig her than 1.2v for 7us, the i c triggers th e fault mode. at fault mo de, the outputs of the gate drivers gl and gr are disabled, the pwmout signal is pulled dow n and th e comp capacitor is discharged by a 30ua sourcing curr ent. the fau l t timer is started. an 8ua current source charges the ft capacitor, and when ft voltage hits 2.38 v, system recovers. it en ables the o u tput drivin g signals, re le ases the comp, resets the fault flag and pulls do wn the ft pin.
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 10 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. appli c ation information pin 1 (ovp) : over voltage protection: this pin is used for over voltage protection. t he output voltage is monitored by this pin and when the voltage o n this pin exceeds 2.38v for 7us, the fault mode i s triggered. pin 3 (ssd) : short string detection: this pin is used for sh ort string prote c tion, when the voltage on this p i n gets lower t han 2.36v for 7us, the i c treats it a s short string condition and triggers the fault mode. pin 4 (fb): led current feedback. this pin is used for led current reg u lation. th e voltage on this pin is regulated with 0.6v average value. fb pin also functions a s short st in g protection . when the voltage on f b gets high er than 1.2 v for 7us, the i c triggers th e fault mode. pin 5 (comp): t h i s pi n i s u s ed f o r c o mp en sa ti on . co nn ec t a 1~47 nf ca p a cito r f r om comp to gnd. t h i s c a p should be x 7 r ceramic. the valu e of this ca p determines the stability of the led current regulation. pin 6 (ft): connect a capacitor from this pin to gnd to set the fault timer. it sets the time to recover the system when a fault condition is detected. ft ft 2. 38 v c t 8u a = a 10nf capacitor on ft sets the delay time around 3ms pin 8 (fset ): connect a resistor from this pin to gnd to set the operating frequency (f o ). the value for this resistor r1 is calculated by 9 o 1. 25 10 r1 f = for r1 = 25k ? , operating frequency will b e 50khz. pin 7 (pwmout): this pin out puts the bur st dimming signal to th e led for fa st pwm di mming. co nnect this pin directly to t he gate of t he dimming mosf et in series of the led. pin 10 (pwmin): this pin is used for bur st brightness control. f o r dc input burst dimming, the dc voltage on thi s pin controls the burst percentage o n t h e o u t p u t . the si gnal is filtered f o r op timal operation. a voltage ranging fro m 0 to 1.2v on pwmin programs t h e burst dimming duty cycle from 0 to 100%. for direct pwm burst di mming, pull bfs high t o vcc throu gh a 20k ? resistor and conn ect pwmin pin to a logic level pwm signal. logic high is burst on and a logic low is burst off. pin 9 (bfs): bfs pin is used to set the burst dimmin g frequency. connect a resistor (r bfs ) in parallel with a capa citor (c bfs ) on this pin t o set t he bu rst dimming fre quency, as shown in fig u re 3. bfs 2.4v 3. 5 5 v burst dimming signal i le d burst dimming frequency rising time figure 3?burst mode with dc input voltage at pwmin pin these values are deter mined as follows: set a percentage of the rising time, where: r is e rise b u rst dt f = r bfs and c bfs are determined by: bf s rise 1 r 2 1.16 k 1 21.43 k d ?? ? + ?? ??
MP4651?off line led driver MP4651 rev.1.0 www.monolithicpower.com 11 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. rise bf s bu r s t b fs 1d c f r 0. 405 ? = for d rise = 0.1, f burst = 200hz, then r bfs = 212k, c bfs = 52nf for direct p w m burst dimming, pull bfs high to vcc throug h a 20k ? re sistor and a pply the pwm signal to p w min pin. pin 2 (sync): burst frequency synchronization. this pin is use d to synchronize the b u rst dimming frequency. applying a synchronizin g frequency signal with small pulse will synchro nize the bur st frequency. syn c en fb vc c bf s fs e t ft gn d gl pw m o u t vi n gr ov p pwm i n co m p 1 2 3 4 5 6 7 8 MP4651 14 15 16 ssd 10 11 12 s y nc s i gna l 9 re f 13 a bf s i led b u r s t di mm i n g s i gnal 1.2v 3.55v 2.4v syn c s i gn al a figure 4?sy nchronize d dc input burst dimming figure 4 sh ows the synchronized d c input burst dimming. the synchron izing signal is filtered by a high pa ss filter. its r i sing edge is caught an d used for synchronizing the triangle waveform on bfs pin. the synchronizing frequen cy should be higher than that set by bfs pin and the amplitude of the synchronizing sign al should b e higher than 1.4v. table 1?function mo de function pin connec t ion pwm bfs sync burs t mode with dc input voltage 0v to 1.2v c bfs , r bfs gnd burs t mode with dc input voltage and synchroni zin g frequency 0v to 1.2v c bfs , r bfs r,c,d netwo rk burs t mode with external pwm source pwm to vcc throug h 20k ? resi st o r gnd burst brightness polarit y : 100% d u ty cycle a t pwm voltage 1.2v. pin 11 (en): pull this pin high to enable the chip, and pull it low to disable the chip. pin 12 (vin): supply volta ge input. bypass the su pply voltage with a 0.1uf or greater ceramic cap. this ca p should be placed clo s e t o the ic. pin 13 (vcc): this pin pro v ides the gate driver supply voltage, its typical va lue is 9.7v. connect a 1uf or greater ceramic ca pacitor on this pin to bypass th e supply voltage. this voltage is also used to supply the external control circu i t. pin 14(gl), pin 16 (gr): gate driving signals out put. gl and gr are 180 degree pha se shifte d driving sign als. with it s enhanced d r iving capab ility, gl and gr are able to directly drive the externally mosf et in the off- line system through a gate driving transformer. connect two 5 ? resist ors in ser i e s with gl and gr to reduce the emi noise. a 2.2nf y capacitor is recommended to be placed bet ween the primary ref e rence gro und and second ary reference ground.
MP4651?off line led driver notice: t he i n formatio n in this docum ent i s subject to chang e w i t h o u t notice. users sh oul d w a rra nt and gu arante e that third part y int e ll ectu al prop ert y r i g h ts are n o t inf r ing ed u p o n w hen i n tegr atin g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. MP4651 rev. 1. 0 www.mono fbthi c pow e r.com 12 1/13/2011 mps proprietar y information. pate nt protected. un authorized photo c op y and d uplication prohibited. ? 2011 mps. all rights reserved. package informati o n soic16 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0 .150 ( 3.80) 0 .157 (4.00) pin 1 id 0.050(1.27) bsc 0.0 13(0. 33) 0.0 20(0. 51) seating plane 0.0 04(0. 10) 0.010(0.25) 0.38 6( 9.8 0) 0.394(10.00) 0 .053(1 .35) 0.069(1.75) top view front view 0.228 (5.80) 0.244 (6.20) side view 1 8 16 9 recommended land pattern 0.213 (5.40) 0.063 (1.60) 0.050(1.27) 0.024(0.61) note: 1) control d i mension is in i nches. d i mension in bra cket is in millimeter s. 2) pac k age len g t h does not incl ude mold fl ash, protru sion s or ga te bu rrs. 3) pac k age widt h does not in clu d e int e rlea d flash or protru sion s. 4) l e ad copl anar ity ( bottom of leads a f t e r formin g) shal l b e 0 .004" in ches ma x. 5) dr awing conf or ms to jedec ms-012, variat ion ac . 6) dr awing is not to scal e. 0.0 10(0.25) bsc gauge plane

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